Strained channel for depleted channel semiconductor devices

ABSTRACT

A planar semiconductor device including a semiconductor on insulator (SOI) substrate with source and drain portions having a thickness of less than 10 nm that are separated by a multi-layered strained channel The multi-layer strained channel of the SOI layer includes a first layer with a first lattice dimension that is present on the buried dielectric layer of the SOI substrate, and a second layer of a second lattice dimension that is in direct contact with the first layer of the multi-layer strained channel portion. A functional gate structure is present on the multi-layer strained channel portion of the SOI substrate. The semiconductor device having the multi-layered channel may also be a finFET semiconductor device.

BACKGROUND

The present disclosure relates generally to semiconductor devices. Moreparticularly, the present disclosure relates to scaling of semiconductordevices.

In order to be able to make integrated circuits (ICs), such as memory,logic, and other devices, of higher integration density than currentlyfeasible, one has to find ways to further downscale the dimensions offield effect transistors (FETs), such as metal-oxide-semiconductor fieldeffect transistors (MOSFETs) and complementary metal oxidesemiconductors (CMOS). Scaling achieves compactness and improvesoperating performance in devices by shrinking the overall dimensions andoperating voltages of the device while maintaining the device'selectrical properties.

SUMMARY

A method of fabricating a semiconductor device is provided that, in oneembodiment, may begin with providing a replacement gate structure on achannel portion of a semiconductor on insulator (SOI) layer of asemiconductor on insulator (SOI) substrate. The SOI layer has a firstthickness of less than 10 nm. Raised source and drain regions arepresent on opposing sides of the replacement gate structure. Thereplacement gate structure is removed to expose the channel portion ofthe SOI layer of the SOI substrate. The channel portion of the SOI layeris then etched to have a second thickness that is less than the firstthickness. An epitaxially grown semiconductor layer is then deposited onthe channel portion of the SOI layer having the second thickness. Thelattice dimension of the epitaxially grown semiconductor layer isselected to be different from the lattice dimension of the channelportion of the SOI layer to provide a strained channel A functional gatestructure is then formed on the strained channel. In another aspect ofthe present disclosure, a planar semiconductor device is provided havinga strained channel that is fully depleted. In one embodiment, the planarsemiconductor device includes a semiconductor on insulator (SOI)substrate including a semiconductor on insulator (SOI) layer with sourceand drain portions having a thickness of less than 10 nm that areseparated by a fully depleted multi-layered strained channel The fullydepleted multi-layer strained channel of the SOI layer includes a firstlayer with a first lattice dimension that is present on a burieddielectric layer of the SOI substrate, and a second layer of a secondlattice dimension that is in direct contact with the first layer of themulti-layer strained channel. A functional gate structure is present onthe fully depleted multi-layered strained channel.

In yet another aspect of the present disclosure, a method of forming afin field effect transistor (finFET) is provided. In one embodiment, themethod of forming the finFET includes providing at least one finstructure having a first width of less than 20 nm, wherein the at leastone fin structure is composed of a first semiconductor material. Areplacement structure is formed atop a channel portion of the at leastone fin structure. Source and drain regions may be formed on the exposedsidewalls of the at least one fin structure on each side of thereplacement gate structure. The replacement gate structure is thenremoved to expose the channel portion of the at least one fin structure.The channel portion of the at least one fin structure is then etched tohave a second width that is less than the first width. An epitaxiallygrown semiconductor layer is then deposited on the channel portion of atleast one fin structure having the second width. The lattice dimensionof the epitaxially grown semiconductor layer is different than thelattice dimension of the channel portion of the at least one finstructure to provide a strained channel. A functional gate structure isthen formed on the strained channel.

In a further aspect of the present disclosure, a fin field effecttransistor (finFET) is provided that includes a fin structure withsource and drain portions of a first semiconductor material having athickness of less than 10 nm, wherein the source and drain portions ofthe fin structure are separated from one another by a fully depletedmulti-layered strained channel The fully depleted multi-layer strainedchannel of the fin structure includes a first layer of the firstsemiconductor material and a second layer of a second semiconductor thatis in direct contact with the first layer. The first semiconductormaterial has a different lattice dimension than the lattice dimension ofthe second semiconductor material. A functional gate structure ispresent in direct contact with the second layer of the fully depletedmulti-layer strained channel of the fin structure.

DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The following detailed description, given by way of example and notintended to limit the present disclosure solely thereto, will best beappreciated in conjunction with the accompanying drawings, wherein likereference numerals denote like elements and parts, in which:

FIG. 1 is a side cross-sectional view depicting forming a replacementgate structure on an extremely thin semiconductor on insulator (ETSOI)substrate as used in one embodiment of a method of forming a planarsemiconductor device in accordance with the present disclosure.

FIG. 2 is a side cross-sectional view depicting removing the replacementgate structure, and etching the channel portion of the ETSOI layer, inaccordance with one embodiment of the present disclosure.

FIG. 3 is a side cross-sectional view depicting depositing anepitaxially grown semiconductor layer on the channel portion of theETSOI layer, wherein the lattice dimension of the epitaxially grownsemiconductor layer is different than the lattice dimension of thechannel portion of the ETSOI layer to provide a strained channel, inaccordance with one embodiment of the present disclosure.

FIG. 4 is a side cross-sectional view depicting one embodiment offorming a functional gate structure on the strained channel, inaccordance with the present disclosure.

FIG. 5 is a perspective view depicting one embodiment of forming finstructures having a width of less than 20 nm, as used in one embodimentof a method for forming a finFETs device, in accordance with the presentdisclosure.

FIG. 6 is a perspective view depicting forming replacement gatestructures on the fin structures, in accordance with the presentdisclosure.

FIG. 7 is a perspective view depicting one embodiment of forming sourceand drain regions on the exposed sidewalls of the fin structures on eachside of the replacement gate structure, in accordance with oneembodiment of the present disclosure.

FIG. 8 is a perspective view depicting one embodiment of removing thereplacement gate structure, in accordance with the present disclosure.

FIGS. 9A and 9B are side cross-sectional views along section line X-X inFIG. 8 depicting etching the channel portion of the fin structures, inaccordance with one embodiment of the present disclosure.

FIG. 10 is a side cross-sectional view depicting depositing anepitaxially grown semiconductor layer on the etched channel portion ofat least one fin structure depicted in FIG. 9B, in accordance with oneembodiment of the present disclosure.

FIG. 11A is a side cross-sectional view depicting forming a functiongate structure on the epitaxially grown semiconductor layer of thechannel portion of the fin structure, in accordance with one embodimentof the present disclosure.

FIG. 11B is a perspective view of the structure depicted in FIG. 11A.

DETAILED DESCRIPTION

Detailed embodiments of the methods and structures of the presentdisclosure are described herein; however, it is to be understood thatthe disclosed embodiments are merely illustrative of the disclosedmethods and structures that may be embodied in various forms. Inaddition, each of the examples given in connection with the variousembodiments of the disclosure are intended to be illustrative, and notrestrictive. References in the specification to “one embodiment”, “anembodiment”, “an example embodiment”, etc., indicate that the embodimentdescribed may include a particular feature, structure, orcharacteristic, but every embodiment may not necessarily include theparticular feature, structure, or characteristic.

Further, the figures are not necessarily to scale, some features may beexaggerated to show details of particular components. Therefore,specific structural and functional details disclosed herein are not tobe interpreted as limiting, but merely as a representative basis forteaching one skilled in the art to variously employ the methods andstructures of the present disclosure. For purposes of the descriptionhereinafter, the terms “upper”, “lower”, “top”, “bottom”, andderivatives thereof shall relate to the disclosed structures, as theyare oriented in the drawing figures. The terms “overlying”, or“positioned on” means that a first element, such as a first structure,is present on a second element, such as a second structure, whereinintervening elements, such as an interface structure, e.g., interfacelayer, may be present between the first element and the second element.The term “direct contact” means that a first element, such as a firststructure, and a second element, such as a second structure, areconnected without any intermediary conducting, insulating orsemiconductor layers at the interface of the two elements.

Increased charge carrier speed may be achieved using strain basedperformance enhancements in semiconductor devices. As used herein, theterm “semiconductor device” refers to an intrinsic semiconductormaterial that has been doped, that is, into which a doping agent hasbeen introduced, giving it different electrical properties than theintrinsic semiconductor. Doping involves adding dopant atoms to anintrinsic semiconductor, which changes the electron and hole carrierconcentrations of the intrinsic semiconductor at thermal equilibrium.Introducing strain to portions of the semiconductor device increase thecharge carrier speed within the semiconductor device, thereforeincreasing the speed of the semiconductor device.

It has been determined that with further scaling of semiconductordevices and implementation of fully depleted semiconductor devices, thatforming stressor wells within the source and drain regions of thesemiconductor devices does not provide the desired strain basedperformance enhancements. Further, stress liners formed overlyingsemiconductor devices provide diminishing performance benefit withincreasingly scaled pitch. In one embodiment, the methods and structuresdisclosed herein provide enhanced device performance for semiconductordevices formed on ETSOI substrates with fully depleted channel regionsby employing a strained channel.

The term “extremely thin semiconductor on insulator (ETSOI) substrate”denotes a semiconductor on insulator (SOI) substrate, in which thesemiconductor on insulator (SOI) layer (hereafter referred to as“extremely thin semiconductor on insulator (ETSOI) layer”) that ispresent on a buried dielectric layer of the ETSOI substrate has athickness of 15 nm or less. In some embodiments, the SOI layer of theETSOI substrate has a thickness of 10 nm or less. As used herein, theterm “channel” is the region underlying the gate structure and betweenthe source and drain of a semiconductor device that becomes conductivewhen the semiconductor device is turned on. A “fully depleted channel”is an undoped or very lightly doped region, which removes dopants, i.e.,charge carriers, from the channel while the semiconductor device is inthe “off” state. By “very lightly doped” it is meant that the maximumamount of dopant in the channel is no greater than 10¹⁷ atoms/cm³. Insome embodiments, the fully depleted channel extends the entire depth ofthe ETSOI layer in which the channel region is present. By entire depthit is meant that the fully depleted channel extends from the bottomsurface of the gate dielectric of the functioning gate structure to theupper surface of the buried dielectric layer of the ETSOI substrate. Insome embodiments, a fully depleted channel advantageously reduces randomdopant fluctuation (RDF) in the semiconductor device, therebyfacilitating threshold voltage (VDD) scaling and improved mobility forincreased effective current.

In some embodiments, to provide a strained and fully depleted channel inthe ETSOI layer of the ETSOI substrate, the portion of the ETSOI layerthat provides the channel of the device is etched to reduce itsthickness, and an epitaxially grown semiconductor material having adifferent lattice dimension than the ETSOI layer is formed on the etchedportion of the ETSOI layer. It has been determined that fully depletedsemiconductor on insulator (SOI) devices, i.e., semiconductor devicesthat have a fully depleted channel, require that the total channelthickness be kept below a certain value to enable short channel control.For example, and in some embodiments, for short channel control inplanar semiconductor devices including a fully depleted channel in theETSOI layer of an ETSOI substrate, the channel of the device should havea totally thickness of 5 nm or 6 nm or lower. In another example, inwhich the semiconductor device is a finFET including a fully depletedchannel in the ETSOI layer of an ETSOI substrate, to enable shortchannel control, the width of the fin structure composed of the ETSOIlayer may be 10 nm or less.

The methods and structures formed herein employ the use of a replacementgate structure to etch the channel portion of the ETSOI layer followedby epitaxially forming the semiconductor material having the differentlattice structure to produce a strained channel. The use of areplacement gate structure may also be referred to as a gate lastprocess flow. In some embodiments, by employing the gate last processflow, the strained channel may be formed after high temperatureprocessing, ion implantation processing, and recess formation processesthat are used in forming the semiconductor device. Therefore, thestrained channel formed by the methods and structures disclosed hereinis not impacted by the aforementioned device processing, which ifsubjected to the strained channel could cause strain relaxation.

FIGS. 1-4 depict one embodiment of a method of forming a planarsemiconductor device formed on an ETSOI substrate 5. The term “planar”as used to describe a semiconductor device denotes that the direction ofcharge carriers from the source region to the drain region of thesemiconductor device is along a plane that is parallel to the uppersurface of the substrate, wherein the functional gate structure ispresent on the upper surface of the substrate. In one embodiment, theplanar semiconductor device is a field effect transistor. As used hereina “field effect transistor” is a transistor in which output current,i.e., source-drain current, is controlled by the voltage applied to afunctional gate structure. As used herein, the term “source” is a dopedregion in the semiconductor device, in which majority carriers areflowing into the channel As used herein, the term “drain” means a dopedregion in semiconductor device located at the end of the channel, inwhich carriers are flowing out of the transistor through the drain. A“functional gate structure” means a structure used to control outputcurrent (i.e., flow of carriers in the channel) of a semiconductingdevice through electrical or magnetic fields.

FIG. 1 illustrates the results of the processing steps that produce anETSOI substrate 5, in which the ETSOI substrate 5 comprises at least anETSOI layer 20 overlying a buried dielectric layer 15, wherein the ETSOIlayer 20 has a thickness of less than 10 nm. A base semiconductor layer10 may be present underlying the buried dielectric layer 15. The ETSOIlayer 20 and the base semiconductor layer 10 may be composed of the sameor a different semiconductor material.

The semiconductor material that provides the ETSOI layer 20 may be anysemiconducting material including, but not limited to Si, SiC, SiGe,SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, and InP, or any combinationthereof. The semiconductor material of the ETSOI layer 20 typically hasa lattice dimension that when employed with the subsequently formedepitaxially grown semiconductor layer (not shown) will produce a strainin the channel of the semiconductor device that is formed on the ETSOIsubstrate 5. In one embodiment, the semiconductor material that providesthe ETSOI layer 20 is silicon (Si). The semiconductor material thatprovides the ETSOI layer 20 may be thinned to a desired thickness byplanarization, grinding, wet etch, dry etch, oxidation followed by oxideetch, or any combination thereof. One method of thinning thesemiconductor material for the ETSOI layer 20 is to oxidize the siliconby a thermal dry or wet oxidation process, and then wet etch the oxidelayer using a hydrofluoric (HF) acid mixture. This process can berepeated to achieve the desired thickness. In one embodiment, the ETSOIlayer 20 has a first thickness T1 ranging from 1.0 nm to 8.0 nm. Inanother embodiment, the ETSOI 20 has a first thickness T1 ranging from2.0 nm to 6.0 nm. In one example, the ETSOI layer 20 has a firstthickness T1 of 5.0 nm or 6.0 nm. The base semiconductor layer 10 may bea semiconducting material including, but not limited to Si, strained Si,SiC, SiGe, SiGeC, Si alloys, Ge, Ge alloys, GaAs, InAs, InP as well asother MN and II/VI compound semiconductors.

In some embodiments and to provide a fully depleted channel region, thesemiconductor material that provides the ETSOI layer 20 may be anintrinsic semiconductor that is free of n-type or p-type dopant. Themaximum concentration of p-type or n-type dopant that is present in thechannel portion of the ETSOI layer 20 may be limited to 10¹⁷ atoms/cm³.In another embodiment, the maximum concentration of p-type or n-typedopant that is present in the channel portion of the ETSOI layer 20 maybe limited to 10¹⁷ atoms/cm³. It is noted that the present disclosure isnot limited to semiconductor devices having fully depleted channelregions. For example, the channel of the semiconductor device can bedoped if desired. In one embodiment, the channel can have a dopantconcentration of 10¹⁸ atoms/cm³ to 10¹⁹ atoms/cm³ to adjust the desiredthreshold voltage (Vt).

The buried dielectric layer 15 that may be present underlying the ETSOIlayer 20 and atop the base semiconductor layer 10 may be formed byimplanting a high-energy dopant into a bulk semiconductor substrate andthen annealing the structure to form a buried dielectric layer 15. Inanother embodiment, the buried dielectric layer 15 may be deposited orgrown prior to the formation of the ETSOI layer 20. In yet anotherembodiment, the ETSOI substrate 5 may be formed using wafer-bondingtechniques, where a bonded wafer pair is formed utilizing glue, adhesivepolymer, or direct bonding.

Still referring to FIG. 1, a replacement gate structure 30 is formed onthe channel portion of the ETSOI layer 20. As used herein, the term“replacement gate structure 30” denotes a sacrificial structure thatdictates the geometry and location of the later formed functioning gatestructure. The sacrificial material that provides the replacement gatestructure 30 may be composed of any material that can be etchedselectively to the underlying ETSOI layer 20 of the ETSOI substrate 5.In one embodiment, the sacrificial material that provides thereplacement gate structure 30 may be composed of a silicon-containingmaterial, such as polysilicon. Although, the replacement gate structure30 is typically composed of a semiconductor material, the replacementgate structure 30 may also be composed of a dielectric material, such asan oxide, nitride or oxynitride material, or amorphous carbon.

The sacrificial material may be patterned and etched to provide thereplacement gate structure 30. Specifically, and in one example, apattern is produced by applying a photoresist to the surface to beetched, exposing the photoresist to a pattern of radiation, and thendeveloping the pattern into the photoresist utilizing a resistdeveloper. Once the patterning of the photoresist is completed, thesections if the sacrificial material covered by the photoresist areprotected to provide the replacement gate structure 30, while theexposed regions are removed using a selective etching process thatremoves the unprotected regions. Following formation of the replacementgate structure 30, the photoresist may be removed.

At least one dielectric gate spacer (not depicted) may then be formedadjacent to the replacement gate structure 30, i.e., in direct contactwith the sidewall of the replacement gate structure 30. In oneembodiment, the at last one dielectric gate spacer may be formed byusing a blanket layer deposition, such as chemical vapor deposition, andan anisotropic etchback method. The at least one dielectric gate spacermay have a width ranging from 2.0 nm to 15.0 nm, and may be composed ofa dielectric, such as a nitride, oxide, oxynitride, or a combinationthereof. The dielectric gate spacer is optional, and may be omitted.

In some embodiments, extension source regions and the drain region (notshown) may then be formed in the portions of the ETSOI layer 20 that arepresent on opposing sides of replacement gate structure 30. In oneembodiment, the extension source region and the extension drain regionare formed using in situ doping, an ion implantation process, plasmadoping, gas phase diffusion, diffusion from a doped oxide or acombination thereof. The conductivity type of the extension sourceregion and the extension drain region typically dictates theconductivity type of the semiconductor device. As used herein, “p-type”refers to the addition of impurities to an intrinsic semiconductor thatcreates deficiencies of valence electrons. In a silicon-containing ETSOIlayer 20, examples of p-type dopants, i.e., impurities, include but arenot limited to: boron, aluminum, gallium and indium. As used herein,“n-type” refers to the addition of impurities that contributes freeelectrons to an intrinsic semiconductor. In a silicon containing ETSOIlayer 5 examples of n-type dopants, i.e., impurities, include but arenot limited to antimony, arsenic and phosphorous.

FIG. 1 further depicts forming raised source and drain regions 25. Theterm “raised” as used to describe the raised source and drain regions 25means that the lower surface of the raised source and drain regions 25is in direct physical contact with the surface of the ETSOI substrate 5on which the gate dielectric of the functional gates structure ispresent. The raised source and drain regions 25 may be formed using aselective epitaxial growth process. The terms “epitaxial growth and/ordeposition” and “epitaxially formed” mean the growth of a semiconductormaterial on a deposition surface of a semiconductor material, in whichthe semiconductor material being grown has the same crystallinecharacteristics as the semiconductor material of the deposition surface.The fact that the process is selective means that the depositedsemiconductor material grows only on exposed semiconductor regions anddoes not grow on a dielectric, such as silicon oxide. The epitaxialgrowth process may be continued until the raised source and drainregions 25 have a height ranging from 5 nm to 50 nm, as measured fromthe upper surface of the ETSOI substrate 5. Typically, the raised sourceand drain regions 25 are composed of a silicon containing material, suchas silicon, silicon germanium, or silicon doped with carbon (Si:C).

Similar to the extension source and drain regions, the conductivity typeof the raised source and drain regions 25 typically dictates theconductivity type of the semiconductor device. In some embodiments, thedopant that dictates the conductivity type of the raised source anddrain regions 25 is introduced in-situ. By “in-situ” it is meant thatthe dopant that dictates the conductivity type of the raised source anddrain regions 25 is introduced during the process step, e.g., epitaxialdeposition, that forms the raised source and drain regions 25.Alternatively, the dopant that provides the conductivity type of theraised source and drain regions 25 is introduced by ion implantation.The p-type and n-type dopants for silicon containing raised source anddrain regions 25 are similar to the p-type and n-type dopants for theextension source and drain regions. In some embodiments, in which theextension source and drain regions are not formed in the ETSOI layer 20prior to forming the raised source and drain regions 25, the extensionsource and drain regions may be formed after the raised source and drainregions 25 by thermally diffusing the n-type or p-type dopant from theraised source and drain regions 25 into the underlying portion of theETSOI layer 20. In some embodiments, the source and drain regions areactivated by a high temperature anneal, while the replacement gatestructure 30 is present in the structure.

FIG. 1 further depicts forming an interlevel dielectric layer 35overlying the raised source and drain regions 25, and planarizing theinterlevel dielectric layer 35 to be coplanar with an upper surface ofthe replacement gate structure 30. The interlevel dielectric 35 may beselected from the group consisting of silicon-containing materials suchas SiO₂, Si₃N₄, SiO_(x)N_(y), SiC, SiCO, SiCOH, and SiCH compounds; theabove-mentioned silicon-containing materials with some or all of the Sireplaced by Ge; carbon-doped oxides; inorganic oxides; inorganicpolymers; hybrid polymers; organic polymers such as polyamides or SiLK™;other carbon-containing materials; organo-inorganic materials such asspin-on glasses and silsesquioxane-based materials; and diamond-likecarbon (DLC, also known as amorphous hydrogenated carbon, α-C:H).Additional choices for the interlevel dielectric layer 35 include any ofthe aforementioned materials in porous form, or in a foam that changesduring processing to or from being porous and/or permeable to beingnon-porous and/or non-permeable. The interlevel dielectric layer 35 maybe deposited using at least one of spinning from solution, spraying fromsolution, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD),sputter deposition, reactive sputter deposition, ion-beam deposition,and evaporation. Following deposition of the dielectric material for theinterlevel dielectric layer 35, a planarization processes is conductedto provide an upper surface, wherein the upper surface of the interleveldielectric layer 35 is coplanar with the upper surface of thereplacement gate structure 30. The planarization of the interleveldielectric layer 23 may be provided by chemical mechanicalplanarization.

FIG. 2 depicts one embodiment of removing the replacement gate structure30, and etching the channel portion of the ESTOI layer 20 b. Followingetching of the ETSOI layer 20 b, the channel portion of the ESTOI layer20 b has a reduced thickness, i.e., second thickness T2, and the portionof the ETSOI layer 20 a corresponding to the source and drain regions ofthe device has the original thickness, i.e., first thickness T1. Thesecond thickness T2 of the ETSOI layer 20 b in the channel portion 40 ofthe device is less than the first thickness T1 of the ETSOI layer 20 athat corresponds to the source and drain regions.

The etch process for removing the replacement gate structure 30 may be aselective etch. As used herein, the term “selective” in reference to amaterial removal process denotes that the rate of material removal for afirst material is greater than the rate of removal for at least anothermaterial of the structure to which the material removal process is beingapplied. For example, in one embodiment, a selective etch may include anetch chemistry that removes a first material selectively to a secondmaterial by a ratio of 100:1 or greater. The replacement gate structure30 may be removed using a wet or dry etch process. In one embodiment,the replacement gate structure 30 is removed by reactive ion etch (RIE).In one example, an etch step for removing the replacement gate structure30 can include an etch chemistry for removing the replacement gatestructure 30 selective to the ETSOI layer 20 b of the ETSOI substrate 5.When composed of polysilicon, the replacement gate structure 30 may beremoved using etch chemistries, such as HBr, SF₆, and NH₄OH.

In some embodiments in which dielectric gate spacers have not beenformed on the sidewalls of the replacement gate structure 30, followingremoval of the replacement gate structure 30, and prior to etching thechannel portion of the ESTOI layer 20 b, dielectric spacers 36 areformed on the sidewalls of the opening that are provided by the exposedsurfaces of the raised source and drain regions 25. In one embodiment,the dielectric spacers 36 may be formed by using a blanket layerdeposition, such as chemical vapor deposition, and an anisotropicetchback method. The dielectric spacers 36 may have a width W1 rangingfrom 2.0 nm to 15.0 nm, and may be composed of a dielectric, such as anitride, oxide, oxynitride, or a combination thereof. The dielectricspacers 36 are optional, and may be omitted.

FIG. 2 depicts etching the channel portion of the ESTOI layer 20 b thatis exposed by removing the replacement gate structure 30. In oneembodiment, the channel portion of the ESTOI layer 20 b is etched with ahalide based gas. A “halide based gas” is a chemical compound of ahalogen with a more electropositive element or group in a gaseous phase.Halogens or halogen elements are a series of nonmetal elements fromGroup 17 IUPAC Style (formerly: VII, VIIA) of the periodic table ofelements and comprise fluorine (F), chlorine (Cl₂), bromine (Br), andiodine (I). Examples of halide based gasses that are suitable as anetchant for etching the channel portion of the ESTOI layer 20 b includechlorine gas (Cl₂), hydrogen fluoride (HF), hydrogen chloride (HCl),hydrogen bromide (HBr) and combinations thereof.

In one embodiment, the halide based gas that etches the channel portionof the ESTOI layer 20 b further includes a carrier gas. For example, thecarrier gas may be hydrogen (H₂), helium (He), argon (Ar) or nitrogen(N₂) gas. The carrier gas may comprise greater than 85% by volume of thehalide based gas flow. In another embodiment, the carrier gas maycomprise greater than 90% by volume of the halide based gas flow. In oneembodiment, the gas flow is comprised of 90% by volume or greater of acarrier gas, such as hydrogen, 1% to 10% by volume of a halide basedgas, such as hydrochloric acid (HCl).

In one embodiment, the halide based gas is applied to the channelportion of the ESTOI layer 20 b at a flow rate ranging from 10 sccm to20 slm. In another embodiment, the halide based gas is applied to thechannel portion of the ESTOI layer 20 b at a flow rate ranging from 100sccm to 300 sccm. The time period for applying the halide based gas istypically greater than 2 seconds. In one embodiment, the time period forapplying the halide based gas may range from 2 seconds to 600 seconds.In another embodiment, the time period for applying the halide based gasranges from 30 seconds to 200 seconds. It is noted that the above flowrates are provided for illustrative purposes only and are not intendedto limit the present disclosure.

Following etching of the channel portion of the ESTOI layer 2 b, thesecond thickness T2 of the remaining portion of the ETSOI layer 20 b mayrange from 1 nm to 4 nm. In another embodiment, the second thickness T2of the channel portion of the ESTOI layer 20 b ranges from 1 nm to 3 nm.In one example, the second thickness of the ETSOI layer 20 b is equal to2 nm. The first thickness T1 of the portion of the ETSOI layer 20 a thatcorresponds to the source and drain regions ranges from 1.0 nm to 8.0nm. In another embodiment, the portion of the ETSOI layer 20 acorresponding to the source and drain region of the device has a firstthickness T1 that ranges from 2.0 nm to 6.0 nm.

FIG. 3 depicts depositing an epitaxially grown semiconductor layer 45 onthe channel portion of the ESTOI layer 20 b, wherein the latticedimension of the epitaxially grown semiconductor layer 45 is differentthan the lattice dimension of the channel portion 40 of the ETSOI layer20 a to provide a strained channel. The terms “epitaxial growth and/ordeposition” and “epitaxially formed and/or grown” mean the growth of asemiconductor material on a deposition surface of a semiconductormaterial, in which the semiconductor material being grown has the samecrystalline characteristics as the semiconductor material of thedeposition surface. In an epitaxial deposition process, the chemicalreactants provided by the source gasses are controlled and the systemparameters are set so that the depositing atoms arrive at the depositionsurface of the semiconductor substrate with sufficient energy to movearound on the surface and orient themselves to the crystal arrangementof the atoms of the deposition surface. Thus, an epitaxial filmdeposited on a {100} crystal surface will take on a {100} orientation.If, on the other hand, the wafer surface has an amorphous surface layer,the depositing atoms have no surface to align to, resulting in theformation of polycrystalline or amorphous silicon instead of singlecrystal silicon. The temperature for epitaxial silicon depositiontypically ranges from 550° C. to 900° C. Although higher temperaturetypically results in faster deposition, the faster deposition may resultin crystal defects and film cracking.

In one embodiment, the epitaxially grown semiconductor layer 45 may becomposed of silicon-containing material. A number of different sourcesmay be used for the deposition of epitaxial silicon. In someembodiments, the silicon containing gas sources for epitaxial growthinclude silane (SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), tetrasilane(Si₄H₁₀), hexachlorodisilane (Si₂Cl₆), tetrachlorosilane (SiCl₄),dichlorosilane (Cl₂SiH₂), trichlorosilane (Cl₃SiH), methylsilane((CH₃)SiH₃), dimethylsilane ((CH₃)₂SiH₂), ethylsilane ((CH₃CH₂)SiH₃),methyldisilane ((CH₃)Si₂H₅), dimethyldisilane ((CH₃)₂Si₂H₄),hexamethyldisilane ((CH₃)₆Si₂) and combinations thereof. The temperaturefor epitaxial silicon deposition typically ranges from 250° C. to 900°C.

In another embodiment, the epitaxially grown semiconductor layer 45 maybe composed of germanium (Ge). A number of different sources may be usedfor the deposition of epitaxial germanium. In some embodiments, thegermanium containing gas sources for epitaxial growth include germane(GeH₄), digermane (Ge₂H₆), halogermane, dichlorogermane,trichlorogermane, tetrachlorogermane and combinations thereof.

In yet another embodiment, the epitaxially grown semiconductor layer 45is composed of a germanium-containing material, such as silicongermanium (SiGe). A number of different sources may be used for thedeposition of epitaxial silicon germanium. In some embodiments, the gassource for the deposition of epitaxial SiGe may include a mixture ofsilicon containing gas sources and germanium containing gas sources. Forexample, an epitaxial layer of silicon germanium may be deposited fromthe combination of a silicon gas source that is selected from the groupconsisting of silane, disilane, trisilane, tetrasilane,hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane,methylsilane, dimethylsilane, ethylsilane, methyldisilane,dimethyldisilane, hexamethyldisilane and combinations thereof, and agermanium gas source that is selected from the group consisting ofgermane, digermane, halogermane, dichlorogermane, trichlorogermane,tetrachlorogermane and combinations thereof. The germanium content ofthe epitaxial layer of silicon germanium may range from 5% to 90%, byatomic weight %. In another embodiment, the germanium content of theepitaxial layer of silicon germanium may range from 10% to 40%.

In an even further embodiment, the epitaxially grown semiconductor layer45 is composed of silicon doped with carbon (Si:C). The carbon (C)content of the epitaxial grown silicon doped with carbon may range from0.3% to 5%, by atomic weight %. In another embodiment, the carboncontent of the epitaxial grown silicon doped with carbon may range from1% to 2.7%.

In one embodiment, the epitaxially grown semiconductor layer 45 has athickness T3 ranging from 1 nm to 4 nm. In another embodiment, thethickness T3 of the epitaxially grown semiconductor layer 45 ranges from1 nm to 3 nm. In one example, the thickness T3 of the epitaxially grownsemiconductor layer 45 is equal to 2 nm. In some embodiments, thethickness of the epitaxially grown semiconductor layer 45 is selected sothat the upper surface of the epitaxially grown semiconductor layer 45is coplanar with the upper surface of the portion of the ETSOI layer 20a corresponding to the source and drain regions of the semiconductordevice, i.e., the portions of the ETSOI layer 20 a having the firstthickness T1.

In some embodiments, when the semiconductor device being formed is ap-type conductivity semiconductor device, such as a p-type field effecttransistor (pFET), the material of the epitaxially grown semiconductorlayer 45 is selected so that the mismatch between the lattice dimensionof the channel portion of the ESTOI layer 20 b and the epitaxially grownsemiconductor layer 45 provides a compressively strained channel. Insome embodiments and to provide a compressively strained channel region,the material of the epitaxially grown semiconductor layer 45 is selectedto have a greater lattice dimension than the lattice dimension of thechannel portion of the ESTOI layer 20 b. For example, when the channelportion of the ESTOI layer 20 b is composed of silicon (Si), anepitaxially grown semiconductor layer 45 composed of silicon germanium(SiGe) or germanium (Ge) provides a compressively strained channelregion. In one example, the compressive strain on the channel of thesemiconductor device produced by the combination of a silicon (Si) ETSOIlayer 20 b and a silicon germanium (SiGe) or germanium (Ge) epitaxiallygrown semiconductor layer 45 may have a magnitude ranging from 100 MPato 1000 MPa. In another example, the compressive strain on the channelof the semiconductor device has a magnitude ranging from 300 MPa to 400MPa. Compressive strain increases the speed of hole charge carriers, andtherefore provides performance enhancements, such as increased switchingspeed, in p-type semiconductor devices.

In some embodiments and when the semiconductor device being formed is ann-type conductivity semiconductor device, such as an n-type field effecttransistor (nFET), the material of the epitaxially grown semiconductorlayer 45 is selected so that the mismatch between the lattice dimensionof the channel portion of the ESTOI layer 20 b and the epitaxially grownsemiconductor layer 45 provides a tensile strained channel. In someembodiments and to provide a tensile strained channel, the material ofthe epitaxially grown semiconductor layer 45 is selected to have asmaller lattice dimension than the lattice dimension of the channelportion of the ESTOI layer 20 b. For example, when the channel portionof the ESTOI layer 20 b is composed of silicon (Si), an epitaxiallygrown semiconductor layer 45 composed of silicon doped with carbon(Si:C) provides a tensile strained channel. In one example, the tensilestrain on the channel of the semiconductor device produced by thecombination of a silicon (Si) ETSOI layer 20 b and a silicon doped withcarbon (Si:C) epitaxially grown semiconductor layer 45 may have amagnitude ranging from 100 MPa to 1500 MPa. In another example, tensilestrain on the channel may have a magnitude ranging from 300 MPa to about400 MPa. Tensile strain increases the speed of electron charge carriers,and therefore provides performance enhancements, such as increasedswitching speed, in n-type semiconductor devices.

FIG. 4 depicts forming a functional gate structure 50 on the strainedchannel that is provided by the combination of the channel portion ofthe ESTOI layer 20 b and the epitaxially grown semiconductor layer 45.The combination of the channel portion of the ESTOI layer 20 b and theepitaxially grown semiconductor layer 45 is hereafter referred to as afully depleted multi-layered strained channel portion 55 of the ETSOIlayer 20 a, 20 b. The channel is fully depleted, because there aresubstantially no charge carriers within the channel portion of thedevice when the device is in the “off” state. The functioning gatestructure 50 that is present on the fully depleted multi-layeredstrained channel portion 55 of the ETSOI layer 20 a, 20 b may include atleast one gate dielectric 51 and at least one gate conductor 52.

The at least one gate dielectric 51 may be composed of any dielectricmaterial including oxides, nitrides and oxynitrides. In one embodiment,the at least one gate dielectric 51 may be provided by a high-kdielectric material. The term “high-k” as used to describe the materialof the at least one gate dielectric 51 denotes a dielectric materialhaving a dielectric constant greater than silicon oxide (SiO₂) at roomtemperature (20° C. to 25° C.) and atmospheric pressure (1 atm). Forexample, a high-k dielectric material may have a dielectric constantgreater than 4.0. In another example, the high-k gate dielectricmaterial has a dielectric constant greater than 7.0. In an even furtherexample, the dielectric constant of the high-k dielectric material maybe greater than 10.0. In one embodiment, the at least one gatedielectric 51 is composed of a high-k oxide such as, for example, HfO₂,ZrO₂, Al₂O₃, TiO₂, La₂O₃, SrTiO₃, LaAlO₃, Y₂O₃ and mixtures thereof.Other examples of high-k dielectric materials for the at least one gatedielectric 51 include hafnium silicate, hafnium silicon oxynitride orcombinations thereof.

In one embodiment, the at least one gate dielectric 51 may be depositedby chemical vapor deposition (CVD). Variations of CVD processes suitablefor depositing the gate dielectric 51 include, but are not limited to:Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD), PlasmaEnhanced CVD (EPCVD), Metal-Organic CVD (MOCVD) and combinationsthereof. In one embodiment, the at least one gate dielectric 51 may bedeposited using a conformal deposition method. The term “conformal”denotes a layer having a thickness that does not deviate from greaterthan or less than 20% of an average value for the thickness of thelayer. In one embodiment, the at least one gate dielectric 51 isdeposited on the fully depleted multi-layered strained channel portion55 of the ETSOI layer 20 a, 20 b as well as the surfaces of the raisedsource and drain regions 25 that are exposed by removing the replacementgate structure. In one embodiment, the thickness of the at least onegate dielectric 51 is greater than 0.8 nm. More typically, the at leastone gate dielectric 51 has a thickness ranging from about 1.0 nm toabout 6.0 nm.

In a following process step, the at least one gate conductor 52 isformed on the at least one gate dielectric 51. The at least one gateconductor 52 may be formed by a deposition process, such as CVD,plasma-assisted CVD, plating, and/or sputtering, followed byplanarization. In one embodiment, the at least one gate conductor 52 iscomposed of metal or a doped semiconductor. Examples of metals that maybe employed for the at least one gate conductor 52 may include, but isnot limited to, W, Ni, Ti, Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, and Re,and alloys thereof. One example of a doped semiconductor that issuitable for the at least one gate conductor 52 is doped polysilicon.

FIGS. 5-11B depict one embodiment of a method of fabricating a finFETsemiconductor device that includes a fully depleted multi-layer strainedchannel. In one embodiment, the method may include providing at leastone fin structure 305 a, 305 b having a first width W1 _(a) of less than20 nm, wherein the at least one fin structure 305 a, 305 b is composedof a first semiconductor material. As used herein, the term “finstructure” refers to a semiconductor material, which is employed as thebody of a semiconductor device, in which the gate structure ispositioned around the fin structure such that charge flows down thechannel on the two sidewalls of the fin structure and optionally alongthe top surface of the fin structure. In one embodiment, the finstructures 305 a, 305 b, and the dielectric layer 150 that the finstructures 305 a, 305 b are present on, may be provided from an SOIsubstrate, in which the SOI layer of the ETSOI substrate provides thefin structures 305 a, 305 b. One example of an SOI substrate suitablefor forming the fin structures 305 a, 305 b that are depicted in FIG. 5has been described above with reference to FIG. 1. In some embodiments,to provide a fully depleted channel region, the semiconductor materialthat provides the SOI layer that provides the fin structures 305 a, 305b may be an intrinsic semiconductor that is free of n-type or p-typedopant. The maximum concentration of p-type or n-type dopant that ispresent in the portion of the SOI layer that provides the channel of thefinFETs may be limited to 10¹⁷ atoms/cm³ or less. It is noted that thepresent disclosure is not limited to fin structures 305 a, 305 b thatprovide a fully depleted channel. For example, the channel of the finFETdevice can be doped if desired. In one embodiment, the channel of thefinFETs can have a dopant concentration of 10¹⁸ atoms/cm³ to 10¹⁹atoms/cm³ to adjust the desired threshold voltage (Vt).

In one embodiment and prior to etching the SOI substrate to provide thefin structure 305 a, 305 b, a layer of the dielectric material can bedeposited atop the SOI substrate to provide a dielectric fin cap 306 a,306 b that is present on the upper surface of each fin structures 305 a,305 b. The material layer that provides the dielectric fin caps 306 a,306 b may be composed of a nitride, oxide, oxynitride material, and/orany other suitable dielectric layer. The material layer that providesthe dielectric fin cap 306 a, 306 b can be formed by a depositionprocess, such as chemical vapor deposition (CVD) and/or atomic layerdeposition (ALD). Alternatively, the material layer that provides thedielectric fin cap 306 a, 306 b may be formed using a growth process,such as thermal oxidation or thermal nitridation. The material layerthat provides the dielectric fin cap 306 a, 306 b may have a thicknessranging from 1 nm to 100 nm.

In one embodiment and following the formation of the layer of dielectricmaterial that provides the dielectric fin cap 306 a, 306 b, aphotolithography and etch process sequence is applied to the materiallayer for the dielectric fin caps 306 a, 306 b and the SOI substrate toform each fin structures 305 a, 305 b. Specifically and in one example,a photoresist mask (not shown) is formed overlying the layer of thedielectric material that provides dielectric fin cap 306 a, 306 b and ispresent overlying the SOI layer of the SOI substrate, in which theportion of the dielectric material that is underlying the photoresistmask provides the dielectric fin caps 306 a, 306 b, and the portion ofthe SOI layer that is underlying the photoresist mask provides the finstructure 305 a, 305 b. The exposed portions of the dielectric materialthat provides dielectric fin cap 305 a, 305 b and the SOI layer, whichare not protected by the photoresist mask, are removed using a selectiveetch process. In one embodiment, each of the fin structures 305 a, 305 bmay have a height H₁ ranging from 5 nm to 200 nm. In another embodiment,each of the fin structures 305 a, 305 b has a height H₁ ranging from 10nm to 100 nm. The fin structures 305 a, 305 b may each have a widthW_(1a) (also referred to as first width W_(1a)) of less than 20 nm. Inone embodiment, the first width W_(1a) of the fin structures 305 a, 305b ranges from 2 nm to 20 nm. In one embodiment, each of the finstructures 305 a, 305 b has a first width W_(1a) ranging from 3 nm to 8nm. In another embodiment, the first width W_(1a) of the fin structures305 a, 305 b ranges from 2 nm to 4 nm. It is noted that any number offin structures 305 a, 305 b may be formed.

FIG. 6 depicts forming a replacement gate structure 310 on the finstructures 305 a, 305 b and the dielectric fin caps 306 a, 306 b.Materials suitable for forming the replacement gate structure 310depicted in FIG. 6 have been described above for the replacement gatestructure 30 that is depicted in FIG. 1. Similar to the replacement gatestructure 30 depicted in FIG. 1, the replacement gate structure 310 thatis depicted in FIG. 6 can be formed utilizing deposition,photolithography and etch process steps. For example, a material layerfor the replacement gate structure 310 may be deposited over the finstructures 305 a, 305 b. Thereafter, a pattern corresponding to thegeometry of the replacement gate structures 310 is formed overlying thedeposited material layer by applying a photoresist to the surface to beetched, exposing the photoresist to a pattern of radiation, and thendeveloping the pattern into the photoresist utilizing a resistdeveloper. Once the patterning of the photoresist is completed, thesections covered by the patterned photoresist are protected while theexposed regions are removed using a selective etching process thatremoves the unprotected regions. In one embodiment, the portion of thematerial layer for replacement gate structure 310 that is removedexposes the sidewalls 51 of the fin structures 305 a, 305 b.

FIG. 7 depicts one embodiment of forming source and drain regions on theexposed sidewalls S1 of the fin structures 305 a, 305 b on each side ofthe replacement gate structure 310. In some embodiment, prior to formingthe source and drain region, spacers 320 may be formed in direct contactwith the replacement gate structure 310. The spacer 320 may be composedof a dielectric material, such as an oxide, nitride or oxynitridematerial. The spacers 320 may be formed using deposition and etchprocesses similar for forming the dielectric gate spacers describedabove with reference to FIGS. 1 and 2. The spacers 320 may have a widthranging from 1 nm to 10 nm, typically ranging from 1 nm to 5 nm.

The source and drain regions may be provided by in-situ dopedepitaxially grown semiconductor material 315 that is formed on thesidewalls S1 of the fm structures 305 a, 305 b. The composition andmethod of depositing the in-situ doped epitaxially grown semiconductormaterial 315 that is depicted in FIG. 7 is similar to the in-situ dopedepitaxially grown semiconductor material that provides the raised sourceand drain regions 25 of the planar device depicted in FIG. 2. N-typefinFET devices may be produced by doping the in-situ doped semiconductormaterial with elements from group V of the Periodic Table of Elements.P-type finFET devices are produced by doping the in-situ dopedsemiconductor material with elements from group III of the PeriodicTable of Elements. In one embodiment, dopant from the in-situ dopedepitaxially grown semiconductor material is diffused into the finstructures 305 a, 305 b to form extension regions for the source anddrain regions. The portion of the fin structures 305 a, 305 b that ispresent between the extension regions is the channel region of thefinFET device. In some embodiments, the source and drain regions areactivated by a high temperature anneal, while the replacement gatestructure 310 is present in the structure.

FIG. 8 depicts one embodiment of removing the replacement gate structure310 to expose the channel portion 325 of the fin structures 305 a, 305b. In one embodiment, prior to removing the replacement gate structure310, an interlevel dielectric layer (not show) is formed having an uppersurface that is coplanar with the replacement gate structure 310. Theinterlevel dielectric layer that is formed on the fin structures 305 a,305 b is similar to the interlevel dielectric layer 35 that has beendescribed above with reference to FIG. 1. Therefore, the compositionsand methods of forming the interlevel dielectric layer 35 depicted inFIG. 1 are suitable for the interlevel dielectric layer that is formedon the fin structures 305 a, 305 b.

The replacement gate structure 310 is removed following the formation ofthe interlevel dielectric layer. Removing the replacement gate structure310 provides an opening to expose the channel portion 325 of the finstructures 305 a, 305 b. In FIG. 8, dielectric fin caps 306 a, 306 b arepresent on the upper surface of the fin structures 305 a, 305 b, but thesidewall of the fin structures 305a, 305b is exposed by removing thereplacement gate structure. The process for removing the replacementgate structure 310 that is depicted in FIG. 8 is similar to the processfor removing the replacement gate structure 30 that is described abovewith reference to FIG. 3.

FIGS. 9A and 9B are cross-sectional views of the fin structures 305 a,305 b including the dielectric fin caps 306 a, 306 b along section lineX-X of FIG. 8. FIGS. 9A and 9B depict one embodiment of etching thechannel portion 325 of the fin structures 305 a, 305 b, wherein the etchprocess reduces the width of the channel portion. More specifically,FIGS. 9A and 9B depict reducing the width of the fin structures 305 a,305 b from their original width W1 _(a) (hereafter referred to as firstwidth W1 _(a)), as depicted in FIG. 9A, to a lesser second width W2_(a), as depicted in FIG. 9B. As indicated above, the first width W_(1a)is typically less than 20 nm. In one embodiment, the first width W_(1a)of the fin structures 305 a, 305 b ranges from 2 nm to 20 nm. In oneembodiment, each of the fin structures 305 a, 305 b has a width W_(1a)ranging from 3 nm to 8 nm. In another embodiment, the first width W_(1a)of the fin structures 305 a, 305 b ranges from 2 nm to 4 nm. Followingetching, the second width W2 _(a) for each of the fin structures 305 a,305 b may range from 2 nm to 10 nm. In another embodiment, the secondwidth W2 _(a) for each of the fin structures 305 a, 305 b followingetching may range from 3 nm to 6 nm. In yet another example, the widthof each of the fin structures 305 a, 305 b may be reduced to a secondwidth W_(2a) ranging from 4 nm to 5 nm. In yet another example, thewidth of each of the fin structures 305 a, 305 b may be reduced to asecond width W_(2a) ranging from 2 nm to 3 nm.

The etch process that reduces the width of the fin structures 305 a, 305b may be an isotropic etch process. Contrary, to an anisotropic etchprocess, an isotropic etch process is non-directional. The etch processapplied to the fin structures 305 a, 305 b that is depicted in FIGS. 9Aand 9B is similar to the etch process that is described above forreducing the thickness of the channel portion of the SOI layer 20 b thatis described above with reference to FIG. 2. Therefore, the descriptionof the etch process that reduces the thickness of the channel portion ofthe SOI layer 20 b that is depicted in FIG. 2 is suitable for describingthe etch process that reduces the width of the fin structures 305 a, 305b that are depicted in FIGS. 9A and 9B. Typically, the etch chemistryfor reducing the width of the fin structures 305 a, 305 b is selectiveto the dielectric fin caps 306 a, 306 b. Similar to the etch process forreducing the thickness of the channel portion of the SOI layer 20 b thatis depicted in FIG. 2, the etch process that reduces the width of thefin structures 305 a, 305 b may include a halide based gas, which mayinclude chlorine gas (Cl₂), hydrogen fluoride (HF), hydrogen chloride(HCl), hydrogen bromide (HBr) and combinations thereof. Further detailson the etch process for reducing the width of the fin structures 305 a,305 b with etch processes employing halide based gasses are describedabove with reference to FIG. 2.

FIG. 10 depicts one embodiment of depositing an epitaxially grownsemiconductor layer 330 on the channel portion 325 of the fin structure305 a, 305 b having the second width W_(2a), in which a latticedimension of the epitaxially grown semiconductor layer 330 is differentthan a lattice dimension of the channel portion 325 of the at least onefin structure 305 a, 305 b to provide a strained channel. Theepitaxially grown semiconductor layer 330 is formed on the exposedsidewalls S3 of the fin structures 305 a, 305 b, but is not formed onthe upper surface of the fin structures 305 a, 305 b that are coveredwith the dielectric fin caps 306 a, 306 b. In one embodiment, theepitaxially formed second semiconductor layer 330 has a thickness T4ranging from 1 nm to 10 nm. In another embodiment, the epitaxiallyformed second semiconductor layer 330 has a thickness T4 that rangesfrom 2 nm to 5 nm.

The epitaxially grown semiconductor layer 330 that is depicted in FIG.10 is similar to the epitaxially grown semiconductor layer 45 that isformed on the channel portion of the ES TOI layer 20 b that is describedabove with reference to FIG. 3. Therefore, the description of thecomposition and the method of forming the epitaxially grownsemiconductor layer 45 that is depicted in FIG. 3 is suitable for theepitaxially grown semiconductor layer 330 that is depicted in FIG. 10.The strain produced by the difference in lattice structure has also beendescribed above with reference to FIG. 3. In one example, epitaxiallygrown semiconductor layers 330 composed of silicon germanium (SiGe) aredeposited on channel portions 325 of fin structures 305 a, 305 bcomposed of silicon (Si) to provide a compressively strained channelsthat are suitable for increasing carrier speed in p-type finFETs(pfinFETs). In another example, epitaxially grown semiconductor layers330 composed of silicon doped with carbon (Si:C) are deposited onchannel portions 325 of fin structures 305 a, 305 b composed of silicon(Si) to provide a tensile strained channel that is suitable forincreasing carrier speed in n-type finFETs (nfinFETs).

The strained channel that is produced by the etched channel portion 325of the fin structures 305 a, 305 b and the epitaxially grownsemiconductor layer 330 are hereafter collectively referred to as afully depleted multi-layer strained channel The channel is fullydepleted, because there are substantially no charge carriers within thechannel portion of the device when the device is in the “off” state. Inthe embodiments, in which the finFET is a p-type conductivity finFET,the compressive strain on the fully depleted multi-layer strainedchannel may range from 100 MPa to 1500 MPa, and in some examples mayrange from 300 MPa to 400 MPa. In the embodiments, in which the finFETis an n-type conductivity finFET, the tensile strain on the fullydepleted multi-layer strained channel may range from 100 MPa to 1000MPa, and in some examples may range from 300 MPa to 400 MPa. It is notedthat the above strain levels are provided for illustrative purposesonly, and it is not intended for the present disclosure to be limited toonly these ranges. The strain in the channel can be quite high dependingupon the lattice mismatch. For example, with 20% silicon germanium(SiGe) on silicon (Si), the strain will be about 1.3 GPa.

FIGS. 11A and 11B depict forming a functional gate structure 335 on thefully depleted multi-layer strained channel of the fin structures 305 a,305 b. In one embodiment, the functional gate structure 335 is formed indirect contact with the sidewall surfaces of the fully depletedmulti-layer strained channel of the fin structures 305 a, 305 b. In oneembodiment, each functional gate structure 335 includes at least onegate dielectric 336 that is present on, e.g., in direct contact with,the fin structures 305 a, 305 b, and at least one gate conductor 337that is present on the at least one gate dielectric 336. Referring toFIG. 11B, the functional gate structure 335 may also include a gatedielectric cap 338 that is present on an upper surface of the at leastone gate conductor 337. The at least one gate dielectric 336 istypically positioned on at least a portion of the sidewalls of the finstructures 305 a, 305 b, but may also be formed in direct contact withthe dielectric fin caps 306 a, 306 b on the upper surface of the finstructures 305 a, 305 b. The functional gate structure 335 may be formedby forming blanket material layers for the at least one gate dielectric336, the at least one gate conductor 337, and gate dielectric cap 338 toprovide a gate stack, and patterning and etching the gate stack toprovide the functional gate structures 335. The functional gatestructure 335 that is depicted in FIGS. 11A and 11B is similar to thefunctional gate structure 50 that is described with reference to FIG. 4.Therefore, further details regarding the compositions for the at leastone gate dielectric 336, and the at least one gate conductor 337 for thefunctional gate structure 335 depicted in FIGS. 11A and 11 B have beendescribed above for the at least one gate dielectric 51 and the at leastone gate conductor 52 that have been described above with reference toFIG. 4.

While the present disclosure has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. A method of fabricating a semiconductor device comprising: providinga replacement gate structure on a channel portion of a semiconductor oninsulator (SOI) layer of a semiconductor on insulator (SOI) substrate,wherein the SOI layer has a first thickness of less than 15 nm. formingraised source and drain regions on opposing sides of the replacementgate structure; removing the replacement gate structure to expose thechannel portion of the SOI layer of the SOI substrate; etching thechannel portion of the SOI layer to a second thickness that is less thanthe first thickness; depositing an epitaxially grown semiconductor layeron the channel portion of the SOI layer having the second thickness,wherein a lattice dimension of the epitaxially grown semiconductor layeris different than a lattice dimension of the channel portion of the SOIlayer to provide a strained channel; and forming a functional gatestructure on the strained channel.
 2. The method of claim 1, wherein theSOI layer has a first thickness that ranges from 2 nm to 10 nm.
 3. Themethod of claim 1, wherein the forming of the raised source and drainregions on opposing sides of the replacement gate structure comprisesepitaxial growth of an in-situ doped semiconductor material.
 4. Themethod of claim 1, wherein the removing of the replacement gatestructure to expose the channel portion of the SOI layer of the SOIsubstrate comprises selective etching, wherein the selective etchingremoves the material of the replacement gate structure selectively tothe raised source and drain regions and the channel portion of the SOIlayer.
 5. The method of claim 1 further comprising forming dielectricspacers on sidewalls of the raised source and drain regions that areexposed by removing the replacement gate structure.
 6. The method ofclaim 1, wherein the etching of the channel portion of the SOI layercomprises a halide gas comprising a hydrogen chloride (HCl) gas, achlorine (Cl₂) gas or a combination thereof.
 7. The method of claim 1,wherein the second thickness of the channel portion of the SOI layerranges from 1.0 nm to 5.0 nm, and the epitaxially grown semiconductorlayer has a thickness that ranges from 1.0 nm to 5.0 nm.
 8. The methodof claim 1, wherein the raised source and drain regions are doped to ap-type conductivity, the channel portion of the SOI layer having thesecond thickness is silicon, and the epitaxially grown semiconductorlayer is silicon germanium (SiGe), or the raised source and drainregions are doped to an n-type conductivity, the channel portion of theSOI layer having the second thickness is silicon, and the epitaxiallygrown semiconductor layer is silicon doped with carbon (Si:C). 9-25.(canceled)